Integrated device technology depends heavily on the use of metallization layers and the patterning of such layers on semiconductor and insulator materials; typically, such materials are doped or undoped silicon, gallium arsenide, other binary, ternary, or quaternary III-V or II-VI semiconductor materials, or insulator materials such as, e.g., silica, alumina, and polymeric layers. Familiar metallization materials may be selected, e.g., from the group of noble metals; see, e.g.,
U.S. Pat. No. 3,881,884, issued May 6, 1975 to H. C. Cook et al, disclosing the manufacture of a composite conductive layer comprising an exposed layer of gold, platinum, palladium, iridium, rhodium, ruthenium, or osmium, underlying non-noble conductor material being separated from an insulating substrate by means of a titanium anti-diffusion layer.
A method for patterning a multi-layer metallization of platinum, palladium, rhodium, ruthenium, osmium, or iridium is disclosed in
U.S. Pat. No. 3,657,029, issued Apr. 18, 1972 to C. R. Fuller; there, a layer of titanium or chromium is used as a mask material.
Popular also is the use of aluminum and aluminum alloys as relatively inexpensive alternatives to noble metals; for example,
U.S. Pat. No. 4,017,890, issued Apr. 12, 1977 to J. K. Howard et al. discloses aluminum and aluminum-copper conductor stripe metallizations.
Typically, when aluminum or aluminum alloys are used for silicon device metallization, a contact material is placed between doped silicon source regions, doped silicon drain regions, and silicon oxide gate regions on the one hand, and the aluminum-containing interconnect metallization. Moreover, it has been found desirable to interpose an interface material between contact and interconnect metallizations; such interface material has desirably low resistivity and acts as a barrier against interdiffusion during device manufacture.